1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming gate structures for transistors with multiple work function values and various integrated circuit products containing such transistors.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices.
Field effect transistors, whether an NMOS or a PMOS device, typically include a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For an NMOS device, if there is no voltage (or a logically low voltage) applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage (or logically high voltage) is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. For a PMOS device, the control voltages are reversed. Field effect transistors may come in a variety of different physical shapes, e.g., so-called planar FET devices or so-called 3D or FinFET devices.
For many decades, planar FET devices were the dominant choice for making integrated circuit products due to the relatively easier manufacturing methods that are used to form such planar devices as compared to the manufacturing methods involved in forming 3D devices. To improve the operating speed of planar FETs, and to increase the density of planar FETs on an integrated circuit device, device designers have greatly reduced the physical size of planar FETs over the years. More specifically, the channel length of planar FETs has been significantly decreased, which has resulted in improving the switching speed of planar FETs. However, decreasing the channel length of a planar FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain regions makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain region. This is sometimes referred to as so-called short channel effects, wherein the characteristic of the planar FET as an active switch is degraded.
As noted above, in contrast to a planar FET, a so-called 3D or FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed in a semiconductor substrate and a gate structure (gate insulation layer plus the gate electrode) is positioned around both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin, become a conductive channel region thereby allowing current to flow. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
For many early device technology generations, the gate structures of most transistor elements has been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon (TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
In manufacturing modern integrated circuit products, transistor devices are sometimes intentionally formed so as to exhibit different threshold voltage levels. In general, a transistor having a relatively lower threshold voltage will operate at a higher switching speed than that of a corresponding transistor with a relatively higher threshold voltage level. Such “low-Vt” (LVT) transistor devices are typically employed in portions of an integrated circuit product where device performance or speed is desirable or critical, e.g., in the logic circuits of an integrated circuit product. Unfortunately, such low-Vt devices tend to exhibit more off-state leakage currents, which means that they consume more power than would otherwise be desired. Thus, all other things being equal, such low-Vt devices are poor choices in applications where reduced power consumption is important, e.g., mobile computing applications, cell phone applications, etc. The opposite is true for so-called “high-Vt” (HVT) transistor devices—they tend to operate at slower switching speeds (a negative) but the off-state leakage currents of such high-Vt devices is less than that of the low-Vt devices (a positive). Such high-Vt devices are typically employed in portions of an integrated circuit product where device performance or speed is less critical, e.g., SRAM circuits. Device designers can also make so-called “regular-Vt” (RVT) transistor devices that have a threshold voltage level that is intermediate to that of the low-Vt devices and the high-Vt devices. Of course, the absolute value of these threshold voltage levels (low, regular and high) may vary depending upon a variety of factors.
Device designers have employed several techniques to intentionally change the threshold voltage levels of transistor devices. One technique simply involves changing the gate length—the distance between the source region and the drain region—of the transistor. All other things being equal, a transistor with a shorter gate length will operate at faster speeds, but it will exhibit higher off-state leakage currents than a corresponding transistor having a larger channel length. Device dimensions have decreased to the point where gate lengths are so small that manufacturing devices with ever smaller gate lengths is very challenging, time-consuming and expensive. Thus, adjusting threshold voltage levels by continuing to reduce the channel length of the transistor devices is becoming more problematic.
Another technique that device designers have used to vary the threshold voltage of transistors involved varying the amount of dopant material used in forming the wells in which the transistors were formed. All other things being equal, the greater the dopant concentration in a well region, the greater will be the threshold voltage of the resulting transistor, and vice-versa. However, in some applications, such as forming FinFET devices, it is very challenging to get the appropriate doping levels, due to random dopant fluctuations and the normal Gaussian distribution of ion implantation processes in general.
Yet another technique that device designers have used to form transistor devices with differing threshold voltage levels simply involves making gate stacks of different materials having different work function values so as to ultimately achieve the desired variation in the threshold voltage levels of the devices. The term “work function” (WF) is commonly used in the art of semiconductor design and manufacturing to refer to the minimum energy needed to remove an electron from the surface of a metal. The work function of a metal is typically a constant characteristic of that metal material and it is usually measured in electron-volts (eV). In general, in CMOS integration schemes using a silicon substrate, a work function metal having a work function near the conduction band edge of silicon (about 4.0 eV) is necessary for NMOS type devices, while a different work function metal having a work function near the valance band edge of silicon (about 5.1-5.2 eV) is necessary for PMOS devices. Thus, in CMOS integration schemes employing high-k gate dielectric materials, at least two types of gate stacks are needed, i.e., a stack of suitable materials that satisfies the individual work function requirements for the PMOS devices and a different stack of materials that satisfies the individual work function requirements for the NMOS devices. As noted above, the gate stack for the PMOS devices provides a flat band voltage closer to the valence band edge of the material of the channel of the PMOS devices, and the gate stack for the NMOS devices provides a flat band voltage closer to the conduction band edge of the material of the channel of the NMOS devices.
By way of example, forming CMOS-based integrated circuit products with dual work function transistor devices might involve depositing a layer of high-k material, e.g., hafnium oxide, that will serve as the gate insulation layer for all of the transistor devices (both PMOS and NMOS) and then depositing a P-work function metal, such as titanium nitride (WF=about 4.9 eV), on the high-k gate insulation layer. Thereafter, the P-work function metal would be patterned so that it is only present on the PMOS devices. Then, an N-work function metal, e.g., an aluminum-based material, such as titanium-aluminum (WF=about 4.3 eV), is deposited above the exposed high-k insulation material (where the NMOS devices will be formed) and above the patterned P-work function metal. After patterning the N-work function metal, the gate stack of the PMOS device is comprised of three layers of material (the high-k gate insulation material, the P-work function metal and the N-work function metal), whereas the gate stack of the NMOS device is comprised of only two layers of material (the high-k gate insulation material and the N-work function metal).
The above-mentioned layer stacking process can be expanded to achieve transistor devices having additional work function levels by simply using the appropriate masking, metal deposition and metal etching steps. For example, to produce an integrated circuit product with transistor devices having three different work function values, the regions of the substrate where the third device will be formed could have been etched so as to clear the gate insulation layer of the P- and N-work function metals described above. Thereafter, a third metal layer, such as tungsten nitride (WF=about 4.6—intermediate that of the P- and N-work function metals) could be deposited above the exposed high-k insulation material (where the third device will be formed) and above the patterned P-work function metal and the patterned N-work function metal. After patterning the third metal layer, the gate stack of the PMOS device is comprised of four layers of material (the high-k gate insulation material, the P-work function metal, the N-work function metal and the third metal layer), the gate stack of the NMOS device is comprised of three layers of material (the high-k gate insulation material, the N-work function metal and the third metal layer) and the gate stack of the third device is comprised of only two layers of material (the high-k gate insulation material and the third metal layer). This process can be applied to obtain four different work functions. In addition to the N- and P-work function metal, one can employ sub-N-work function metals (WF=4.45 eV) and sub-P-work function (WF=4.75 eV) metals. The process explained above can be repeated to integrate a third and a fourth device that has a gate structure including such third and fourth metal layers.
As is readily apparent, the above-mentioned layer stacking process can become quite unwieldy and complex as more and more version of transistor devices with different threshold voltage levels are fabricated. Among other problems, etching of metals tends to be more difficult and the different physical heights of the gate stacks of the various devices can cause problems during subsequent processing operations. As an example, it may be more difficult to achieve a truly planar surface on a layer of material that is deposited above all of the different height gate stacks even if the layer is subjected to one or more chemical mechanical polishing processes. Such a lack of planarity can lead to problems in accurately patterning the deposited layer of material due to depth-of-focus variations when it comes to exposing a layer of photoresist material positioned above the deposited layer.
The present disclosure is directed to novel methods of forming gate structure transistors with multiple work function values and various integrated circuit products containing such transistors that may solve or reduce one or more of the problems identified above.